1. Field of the Invention
The present invention relates to a pre-charge step determining circuit of a generic bit line, particularly for non-volatile memories. More particularly, the invention relates to a circuit for determining the minimum duration of the pre-charge step of a bit line.
2. Discussion of the Related Art
In conventional cycles for reading a non-volatile memory, it is customary to provide, in order to improve the reading activity, time steps that are dedicated to the quick pre-charging of the word and bit lines selected for reading, in order to make them reach their working point and then read the data
Word lines are notoriously capacitive and therefore slow to pre-charge, whereas bit lines have a different behavior, as regards pre-charging, according to the voltage level used in the memory device.
The pre-charge interval is generally determined by a generic delay network that is often adjustable, or the monitoring of a generic word line propagation is provided for by associating the pre-charging end time with the attainment of a preset level by the line.
A circuit for reproducing the propagation of a generic word line of a memory device to achieve faster reading has been the subject of a patent application in the name of the same Applicant as the present application.
Both approaches mentioned above lack the necessary compliance with the operating conditions of the device and therefore result in the oversizing of the time interval meant for the pre-charging step.
In normal supply voltage conditions, 4.5-5.5 V, the greatest slowing effect is caused by the pre-charging of the word lines, since it is necessary to wait for the signal to propagate alone, the entire line (which has natural resistive and capacitive characteristics), whereas the bit lines can be pre-charged relatively quickly.
The situation changes if the memory device is supplied at a low voltage, 2.7-3 V.
At low voltage, the behavior during word line pre-charging remains substantially unchanged, showing only a small delay with respect to operation at normal voltage; the bit line pre-charging step, however, slows down considerably.
With reference to FIG. 4, which illustrates a sense amplifier of the dynamic latch type for data capture, provided with P-type transistors 12 and 12', for fast pre-charging of the nodes of the matrix branch and of the reference branch (which are interchangeable), pre-charge transistors 12 and 12' in fact deliver, at the normal operating voltage, (i.e., approximately 5V) a pulsed pre-charge current that has a high peak.
The sense amplifier of FIG. 4 has been the subject of a patent application in the name of the same Applicant as the present application.
The curve of the pre-charge current is designated by the reference letter "a" in FIG. 1.
In the case of a low operating voltage, transistors 12 and 12' are no longer able to deliver the high pulsed current (pickup current) that is required to quickly trigger pre-charging; therefore, the curve of the pre-charge current changes from curve "a" to curve "b", also shown in FIG. 1.
In this manner, the bit lines are affected by this decrease in current and pre-charge much more slowly.
Therefore, a drawback of this situation is the fact that the factor that limits the pre-charging speed, and therefore the reading speed, of the memory device is now constituted by the behavior of the pre-charging of the bit line.
The chart of FIG. 2 shows, in a Cartesian system whose ordinates plot the current of a memory cell and whose abscissae plot the voltage at the drain terminal of the cell, two curves of the cell current Icell, in case of 5-V voltage (curve "c") and in the case of low voltage, 2.7 V (curve "d").
FIG. 3 instead plots voltages as a function of time and shows the curves that indicate the pre-charging of a generic word line and of a generic bit line in two different voltage conditions, at normal voltage and at low voltage.
The curves "e" and "f" relate respectively to the pre-charge curve of a word line and a bit line, with a voltage equal to 5 V, whereas the curves "g" and "h" relate respectively to the pre-charge curve of a word line, and a bit line with a voltage of 2.7 V.
FIG. 3 indicates, for the various lines, the respective delays that affect them before reaching the working point, starting from the time t.sub.0, which corresponds to the origin of the axes.
The expression .DELTA.t.sub.1 references the delay that affects the bit line "f" at 5 V and .DELTA.t.sub.2 references the delay that affects the word line at the same voltage. It is evident that, at the higher voltage the word line has a greater delay than the bit line, i.e., it has a slower pre-charging.
The reverse case occurs at the lower voltage. The expression .DELTA.t.sub.3 references the delay that affects the word line "g" at low operating voltage and .DELTA.t.sub.4 references the delay that affects the word line "h", again at low voltage.
Therefore, the graph clearly shows that at the lower voltage it is the bit line that slows the reading of the memory device, because its pre-charging is slower than that of the word line.
The cell current during the pre-charge step of the bit line runs the risk of being confused, by overlap, with the pre-charge current of the bit line, shown by the curve "b" in FIG. 1, since the latter has a very similar development because it has lost its pulsed characteristic (with a high peak).
The pre-charge interval that must be selected (with reference again to FIG. 3) to ensure pre-charging of the various lines, therefore, cannot be determined unequivocally so as to meet all possible operating voltages.
Since different behaviors of the word lines and of the bit lines occur at different voltage values, it is necessary to take both of these variables into account in order to determine a pre-charge time interval that is valid in any operating condition and that is not oversized so as to assuredly comply with all possible behaviors of the lines.